Verilog

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Verilog examples and other very interesting...

Verilog LOGIC ANALYZER

Some examples in PLUNIFY CLOUD COMPILER FOR ALTERA AND XILINX !!!

• Parallel Port FPGA Interface with Verilog source

Books

• Pong P. Chu Cleveland State University, FPGA PROTOTYPING BY VERILOG EXAMPLES Xilinx SpartanTM-3Version
  
• at page [43-pdf-paging] or [page-13]

// The ' t i m e s c a l e d i r e c t i v e s p e c i f i e s t h a t
// t h e . s i m u l a t i o n t i m e u n i t i s I ns and
// t h e s i m u l a t i o n timestep i s 10 ps
' t i m e s c a l e 1 ns/lO ps
5
module eq2-testbench ;
// s i g n a l d e c l a r a t i o n
r e g [1:0] test-in0 , test-in1 ;
wire test-out ;
I0
// i n s t a n t i a t e t h e c i r c u i t under t e s t
eq2 uut
(.a(test-inO), .b(test-inl), .aeqb(test-out));
a aeqb
eq2
.b
ii // t e s t v e c t o r g e n e r a t o r
i n i t i a l
begin
// t e s t v e c t o r 1
test-in0 = 2'bOO;
test-in1 = 2'bOO;
# 200;
// t e s t v e c t o r 2
test-in0 = 2'bOl;
test-in1 = 2'bOO;
# 200;
// t e s t v e c t o r 3
test-in0 = Z'b01;
test-in1 = 2'bll;
# 200;
// t e s t v e c t o r 4
test-in0 = Z'b10;
test-in1 = 2'blO;
# 200;
// t e s t v e c t o r 5
test-in0 = 2'blO;
test-in1 = 2'bOO;
# 200;
// t e s t v e c t o r 6
test-in0 = 2'bll;
test-in1 = 2'bll;
# 200;
// t e s t v e c t o r 7
test-in0 = 2'bll;
test-in1 = ZJb01;
# 200;
// s t o p sitnztlation
$ s t o p ;
end
511 endmodule

he code consists of a module instantiation statement, which creates an instance of the 2-
bit comparator, and an initial block, which generates a sequence of test patterns. The initial
block is a special Verilog construct, which is executed once when simulation starts. The
statements inside an initial block are executed sequentially. Each test pattern is generated
by three statements, as in

// test v e c t o r 2
test-in0 = Z'b01;
test-in1 = 2'bOO;
#200;

The first two statements specify the values for the t e s t - i n 0 and t e s t - i n 1 signals 
and the third indicates that the two values will last for 200 time units. 
The last statement, $stop, is a Verilog system function that stops the simulation and returns the control to simulation
software.
The code has no monitor. We can observe the input and output waveforms on a simulator's
display, which can be treated as a "virtual logic analyzer." The simulated timing diagram
of this testbench is shown in Figure 2.16.
Writing code for a comprehensive test vector generator and a monitor requires detailed
knowledge of Verilog. For now, this listing can serve as a testbench template for other combinational
circuits. We can substitute the uut instance and modify the test patterns according
to the new circuit. We provide a review of additional modeling and simulation-related language
constructs and demonstrate the construction of a more sophisticated testbench in
Section 7.5.